1. Field of the Invention
The present invention relates to a MOS type semiconductor device, such as a power vertical MOSFET or a insulated gate bipolar transistor (IGBT), (also referred to as an IGT or COMFET).
2. Description of the Related Art
FIG. 2 is a section view showing the structure of a conventional power vertical MOSFET. A silicon substrate is prepared by forming an N.sup.- drain layer 1 on an N.sup.+ drain layer 2. A P type base layer 3 is then formed on the surface of the N.sup.- drain layer 1. A P.sup.+ diffusion layer 4 is formed in the central portion of the P type base layer 3 to a depth reaching the N.sup.- layer 1. A P.sup.+ diffusion layer 5 is formed in the surface of the P type base layer 3.
N.sup.+ source regions 6 are formed in the P type base layer 3 in such a manner as to leave a section of layer 3 between the N.sup.+ source region 6 and the N.sup.- drain layer 1. The section of the P type base layer 3 which is located between the source region 6 and the N.sup.- drain layer 1 serves as a channel forming region 7. A gate electrode 9 of polycrystalline silicon is formed in a gate insulating film 81 over the channel forming region 7. A source electrode 10 is provided in an insulating film 82 over the gate electrode 9 in such a manner that the source electrode 10 is in contact with the P.sup.+ layers 4 and 5 and the source layer 6 through an opening formed in the insulating film 82.
The right half of FIG. 2 shows the voltage withstanding structure of the end portion of the MOSFET in which a plurality of base layers 3 are formed in the substrate. The gate electrode 9 and the source electrode 10 are extended in the insulating film 83 towards the end portion, thus forming field plates. A guard ring provided as P.sup.+ layer 41, is formed near the end portion to surround the plurality of base layers 3. The P.sup.+ layer 41 is in contact with a peripheral electrode 12 which is equal in potential to a drain electrode 11. The strain produced by cutting the silicon substrate makes the side of the substrate low in resistance. Therefore, the peripheral electrode 12 is equal in potential to the drain electrode 11 without a connecting conductor. The electrode 12 is connected to a gate electrode 91. A wiring electrode 13 is formed on an insulating film 84 over the electrodes 10 and 12.
As is seen from FIG. 3, the wiring electrode 13 is a single line for interfacing to a MOSFET controlling IC 32 which is formed on the same silicon substrate as a MOSFET 31. The signal line is connected to the gate electrode 9 of the MOSFET. When a voltage that is positive with respect to the source electrode 10 is applied to the gate electrode 9, a channel is formed in the channel forming region 7 of the P type base layer 3 below the gate insulating film 81. As a result, electrons are injected into the drain layers 1 and 2 through the channel. The transistor is, thus, rendered conductive. When the gate electrode 9 is made equal in potential to the source electrode 10, or negatively biased, the transistor is rendered non-conductive. As such, the transistor functions as a switching element. If the potential of the drain electrode 11 is higher than the potential of the source electrode 10, the conductivity of the surface layer of the N.sup.- drain layer 1 below the source electrode 10 may be converted into a P type conductivity. However, the conductivity of the surface layer below the electrode 12 is equal in potential to the drain electrode 11 and remains N type. Thus, a developing layer is allowed to extend towards the P+ layer 41, thereby preventing breakdown of the elements, eliminating adverse effects of the substrate end portion, and stabilizing the device.
FIG. 4 shows a conventional IGBT (insulated gate bipolar transistor). In FIG. 4, those parts which have been previously described with reference to FIG. 2 are designated by the same reference numerals. A P.sup.+, drain layer 20 is shown in FIG. 4. The N.sup.- layer 2 between the N.sup.- layer 1 and P.sup.+ layer 20 is a buffer layer. When electrons are injected from the N.sup.+ source region 6 into the P.sup.+ drain layer 20 through the channel forming region 7, the N.sup.- layer 1, and the N.sup.30 buffer region 2, holes are injected from the P.sup.+ drain layer 20 through the N.sup.+ buffer layer 2 into the N.sup.- layer 1. As a result, conductivity modulation occurs in the N.sup.- layer 1 such that the resistance becomes low.
Several problems are apparent in the operation of conventional MOS type semiconductor devices such as described above. FIG. 5 shows the surface region of the end portion of a MOSFET or an IGBT which is near the guard ring. In FIG. 5, those parts which have been previously described with reference to FIGS. 2 and 3 are designated by the same reference numerals. Since the insulating film 83 is interposed between the N.sup.- layer 1 of the silicon substrate and the signal line 13 which extends from above the source layer 3 to above the guard ring, a capacitance 14 is developed between the surface of the silicon substrate and the signal line. As the signal level of the signal line 13 changes, the potential of the surface becomes unstable because of the presence of this capacitance 14. As a result, performance of the device depends on the presence or absence of a potential on the signal line 13.
In an attempt to reduce capacitance 14, the thickness of the insulating film 83 can be increased. However, this method was not proved very effective. Another method for reducing capacitance 14 is shown in FIG. 6. After electrodes 10 and 12 are formed, a resistive film 15 (e.g., an amorphous silicon film) is formed to bridge electrodes 10 and 12. This second method is also disadvantageous. The amorphous silicon film 15, formed by an electron beam vacuum deposition, is low in film resistance control stability, and its formation increases the number of manufacturing steps by requiring a film forming step and a photolithograph step.
FIG. 7 shows a circuit with the MOSFET 71, such as shown in FIG. 2, driving an inductive load L. The case is considered in which the FET 71 is turned ON to energize the inductive load L, such as a motor or relay, and is then turned OFF. When this occurs, it is sometimes possible for a parasitic bipolar transistor made up of the N.sup.+ source layer 6, P type base layer 3 and N.sup.- layer 1 of the MOSFET 71 to be turned ON. This results in the breakdown of the device. This phenomenon is described in detail with reference to FIG. 8.
Referring to FIG. 8, when the MOSFET is turned OFF with the inductive load connected thereto, depletion layers 32 are formed on both sides of the PN junction 31 of the FET. Some of the discharged carriers flow as a hole current 33 through the P type base layer 3 located under the N.sup.+ source layer 6. The surface of the P type base layer 3 is connected through the source electrode 10 to the N.sup.+ source layer 6, so that a potential difference, which is the product of the hole current 33 and the base resistance Rb, is created between the source layer 6 and the base layer 3. If the potential difference exceeds the base/source built-in voltage, then electrons are injected from the source 6, the parasitic bipolar transistor is turned ON, and the device suffers breakdown.
An object of the formation of the P.sup.+ diffusion layer 4 in FIG. 2 is to decease the hole current 33 flowing below the N.sup.+ source layer 6 and thereby prevent breakdown of the device when the parasitic transistor is turned ON. An object of the formation of the P.sup.+ low resistance layer 5 is to decease the base resistance Rb and thereby prevent breakdown of the device by preventing the parasitic transistor from turning ON. However, even with use of these methods, when the drain voltage increases, breakdown occurs at location 34 of the P diffusion layer 3, and great numbers of holes and electrons are formed. As a result, the turn OFF performance of the power MOSFET is insufficient when used with an inductive load.
Similarly, when the IGBT is turned OFF a parasitic bipolar transistor made up of the N.sup.+ source layer 6, P type base layer 3 and N.sup.- layer 1 of the MOSFET 71 is turned ON, resulting in the breakdown of the device. Furthermore, even when the IGBT is "ON", there is a hole current flow 33 below the N.sup.+ region 6. Thus, the IGBT suffers from a difficulty that, even when it is turned OFF with a non-inductive load, or when it is "ON", the parasitic transistor is turned ON, thus resulting in the breakdown of the device. As with the power MOSFET, an effort has been made to eliminate this difficulty in the IGBT by formation of the P.sup.+ diffusion layer 4 and the P.sup.+ low resistance layer 5. However, the difficulty has not been completely eliminated.